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STM32F0 SPI TxFIFO Flush

Question asked by dudka.michal.001 on Nov 10, 2017
Latest reply on May 4, 2018 by Dave S

Hi,

 

i've found simple problem with Tx FIFO in SPI in slave mode. Take a model situation from reference manual (STM32F031) "Figure 281. Slave full-duplex communication". Imagine situation when master stops communication after 1st byte. Master returns NSS to high, slave stops communication but in TxFIFO still remain 2-3 bytes of data ! 

 

Figure 281 suggest  that i should disable SPI with end of communication (rising edge of NSS). But it looks like as illegal operation, datasheet says that correct way to disable SPI needs empty FIFO (FTLVL =0). No matter what i do (disable SPI or not) in FIFO still remains data. And if master will begin any further transmission, it will read these old data from TxFIFO.

 

Is there any legal way how to flush Tx FIFO ? 

 

Now i am using procedure:
- Reset SPI in RCC
- complete init SPI

but it doesnt looks like a legal procedure...

 

thanks,
Michal

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