I have read several documents about the Cache, but the last sentence in AN4839 (Level 1 cache on SRM32F7 Series) confuses me.
" However, If the external device is an ASIC and/or a FIFO, the user must disable the D-cache for reading."
I want to connect a FPFA to 32bit external bus, Addresses start at 0x6000.0000.
If I only look for the access to the FPGA: What is the difference between
A) disabled D-Cache and
B) enabled D-cache and set Memory region in the MPU to sharable, not bufferable and not cacheble?
Disable the D-cache is not an option in my project because this would slow down everything else.
In another thread someone suggested to swap address regions SRAM/SDRAM (0x60000000 <=> 0xC0000000) to change some behaviour.
Does this mean there are some internal attributes bound to the memory regions that cannot be changed via MPU settings?
This is how I would initialize the MPU for access to the FPGA.
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x60000000;
MPU_InitStruct.Size = MPU_REGION_SIZE_64KB;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER1;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.SubRegionDisable = 0x00;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;