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Problem with STM32F765 and SD-Card =>spurious accesses to external bus

Question asked by Gunnar Bohlen on Nov 6, 2017



we have a custom made board with a STM32F765NIHx, Rev. Z with a connection to an SD-Card and 8bit eMMC.

A FPGA is connected via 32bit external bus. We use Keil µVision with their Middleware for the file system.

Writing files to SD and eMMC works fine, we didn't see any problems.

Communication to the FPGA also seems to work fine, we do not see any communication problems.

Then we wanted to log data from the FPGA to SD-card or eMMC. We noticed that we sometimes get invalid data from the FPGA.


We have reduced the test program to a minimum that still shows the problem:

-Initialize board (Pins, directions, Pin Functions)

-Initialite chip select of external 32 bit bus (used to communicat with FPGA)

-NO accesss to the FPGA any more!








With the delay we simulate the time that takes to collect 8kByte data from the FPGA.

We see spurious accesses to the external chip select signal. This access reads or writes to a fifo in the FPGA and adds or removes unwanted data which cause then the problem.


We tried to find out where these exyternal bus accesses come from.

If we disable the chip select from the memory region and the CPU still accesses this memory region, the CPU should generate a hard fault. We verified that the hardfault is generated by modifying a pointer variable. But with our test program we do not get any hard fault. Therefor we assume that the problem is not an invalid access from the CPU


In case there is a DMA access to an invalid address there is (according to the STM user manual) no hard fault, instead the dma should set an error flag.


I tried to find the error condition, but during this test I found out something else which might be related to the problem:

I set a breakpoint in file stm32f7xx_hal_dma.c, function

static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)

In the middleware I have configured a Data Cache Size of 8kBytes

I see that DataLength is 0x2000 which is 8kBytes.

In the DMA configuration register MSIZE and PSIZE is set to 32bit. Is NDT number of bytes (which would be correct) or number of transfers (which could also be be 1/4of 0x2000  because transfer soze is 32bit?)


I set another breakpoint in

void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)


I notice that for each transfer there seems to be a FIFO error. Following code lines are executed.


if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
      /* Clear the FIFO error flag */
      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;


      /* Update error code */
      hdma->ErrorCode |= HAL_DMA_ERROR_FE;

The DMA-Regsster NDT (number of transfers) contains now the value 0xF7FF. I would expect a value of 0.

I don't see a reason for a FIFO error, and the written filesare OK.

Does anyone know about the FIFO Errors, or the NDT register value !=0?

And most important: has anyone else seen unwanted access to the externaml memory regions?


Regards, Gunnar Bohlen