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Question asked by
on Jul 12, 2005
on Jul 12, 2005 by 16536
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Jul 12, 2005 7:24 PM
This is from page 42 of ST10F269 USER’S MANUAL:
Software modifications (implicit or explicit) of the PSW are done in the execute phase of the respective instructions. In order to maintain fast interrupt responses, however, the current interrupt prioritization round does not consider these changes. For example an interrupt request may be acknowledged after the instruction that disables interrupts via IEN or ILVL or after the following instructions. Time critical instruction sequences, therefore, should not begin directly after the instruction disabling interrupts, as shown in the example.
INT_OFF: BCLR IEN ; globally disable interrupts
IN-1 ; non-critical instruction
CRIT_1ST: IN ; start of non-interruptible critical
. . .
CRIT_LAST: IN+x ; end of non-interruptible critical
INT_ON: BSET IEN ; globally re-enable interrupts
It makes no mention of the interrupt disable problem and indicates that only one nop is necessary.
I would hope that there is better source of information on this topic!
I did not intend to start a new topic.
[ This message was edited by: Shep on 12-07-2005 22:57 ]
[ This message was edited by: Shep on 12-07-2005 23:00 ]
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