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How can I reduce time between read cycles on Nand flash (controlled by FMC)

Question asked by Abdul Qadir Shabbir on Oct 31, 2017

Hi, 

I have interfaced S34ML04G2(nand flash) with STM32F723 controller and using built-in FMC controller to read the Nand flash. 

I am using "HAL_NAND_Read_Page_8b()" to read the entire page and have hooked up a logic analyzer on the interface.

I configured the FMC timings as per AN2784 ("Using the high-density STM32F10xxx FSMC peripheral to drive external memories"). 

 

When I read the entire page, I see a huge delay between each byte read (220 - 150ns) {see attached scope capture - #CE1 goes high between each data access}. This is a huge delay in 5ns world (My HCLK is 200MHz). 

 

Essentially the code being executed during the scope capture is: 

 

/* Get Data into Buffer */
for(; index < size; index++)
{
*(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
}

 

My timing settings are:

 

/* hnand1.Init */
hnand1.Init.NandBank = FMC_NAND_BANK3;
hnand1.Init.Waitfeature = FMC_NAND_WAIT_FEATURE_ENABLE;
hnand1.Init.MemoryDataWidth = FMC_NAND_MEM_BUS_WIDTH_8;
hnand1.Init.EccComputation = FMC_NAND_ECC_DISABLE;
hnand1.Init.ECCPageSize = FMC_NAND_ECC_PAGE_SIZE_2048BYTE;
hnand1.Init.TCLRSetupTime = 0;
hnand1.Init.TARSetupTime = 0;
/* hnand1.Config */
hnand1.Config.PageSize = 2048;
hnand1.Config.SpareAreaSize = 128;
hnand1.Config.BlockSize = 64;
hnand1.Config.BlockNbr = 8192;
hnand1.Config.PlaneNbr = 2;
hnand1.Config.PlaneSize = 4096;
hnand1.Config.ExtraCommandEnable = DISABLE;
/* ComSpaceTiming */
ComSpaceTiming.SetupTime = 1;
ComSpaceTiming.WaitSetupTime = 3;
ComSpaceTiming.HoldSetupTime = 2;
ComSpaceTiming.HiZSetupTime = 1;

 

Anyone, who has a hint on who would have caused this delay? Apparently, this is bare metal code, so no clock cycles are lost during execution.

I have enabled the ART and I-cache (when I enable the D-cache, I see a different problem, which I can also discuss if anyone is willing to look )

 

Any help would be greatly appreciated. 

Thanks, 

AQ

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