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FMC synchronous PSRAM - lost AHB transactions

Question asked by leinad on Oct 30, 2017
Latest reply on Nov 1, 2017 by leinad

Hello

I have FPGA with memory mapped peripheral what I would like to control from external STM32 MCU (STM32F767 ). I chose FMC peripheral in synchronous PSRAM mode because communication can be easily implemented in HDL wrapper. I was inexperienced in this stuff so firstly I just connected logic analyzers to FMC bus, made some configuration and did some write accesses "into air".

 

Unfortunately I have faced some problems what I don't understand.

 

My configuration for all PSRAM banks:

DataAddressMultiplex = off;
MemoryType = PSRAM;
MemoryDataWidth = 16b;
BurstAccessMode = on

WriteBurst = on;
Wait signal manage = off
WriteOperation = on;
ExtendedMode = None
ContinuousClock = on
WriteFifo = on;
PageSize = none;

Timing:
AddressSetupTime = 15;
AddressHoldTime = 15;
DataSetupTime = 255;
BusTurnAroundDuration = 15;
CLKDivision = 2;
DataLatency = 2;
AccessMode = MODE_A;

 

First problem is that I'm loosing some AHB requests.

Example code

#define ADDR_PSRAM1        0x60000000 //PSRAM Bank 1

uint32_t wdata[8] = { 0x00010000, 0x00030002, 0x00050004, 0x00070006,
            0x00090008, 0x000B000A, 0x000D000C, 0x000F000E };
uint32_t *pAddr = (uint32_t*) ADDR_PSRAM1;
for (i = 0; i < 8; ++i) {
   *pAddr++ = wdata[i];
   //myDelay();
}

I would expect that I will see 8 FMC write transactions but I saw only first one (sometimes two transactions). I was adding some sw delay (commented myDelay()) which solved the problem but I dont think it's good aproach.

First I had CLKDivision 16 so I though that CPU is too fast for FMC, so I switched division to 2 without noticeable effect.

 

Am I doing something wrong? I suppose FMC peripheral is for FLASH/RAM extension of MCU memory so there should be no problem. Is there some bit where I can check that FMC transactions is done? In reference manual there is information about AHB error flag but it is not useful for me.

 

Second problem is OCCASIONAL "leakage" in FMC transaction from following AHB data "stream". Please see attached pictures (1.png - 6.png). Pictures are screenshots of FMC entries from logic analyzer (see code above).

You can see values of D0-D7, A0-A4, NE1, NADV a CLK signals in FMC transactions. NE1 is basically same as NWE signal. Cursor "C1.2" points at rising edge of clock where low 16b data from 32b value is written. Following rising edge should be remaining high 16b part.

After that NWE/NEx signal should be deasserted acording to reference datasheet but not in my case. You can see in first two pictures (1.png, 2.png) that two 32b AHB transactions were done in one FMC write. Sometimes I observed 3x32b in one FMC operation. Remaining FMC entries are ok from my point of view - values from 0x00090008 to 0x000F000E are written correctly.

This problem doesn't happen when write FIFO is disabled, but I don't know why...I have found nothing about it in reference manual.

 

Can someone please help me?

 

Regards

 

Daniel

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