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STM32F429ZI HS USB: USB_CoreReset() timing out waiting for CSRST == 0

Question asked by Don Starr on Oct 28, 2017
Latest reply on Oct 30, 2017 by Don Starr

Custom board based on STM32F429ZI with Microchip USB3300-EZK HS PHY. The clocks and USB connections modeled on the STM32429I-EVAL1 schematic. I've verified that the CubeMX-generated code for my board looks just like what is generated for the EVAL1. The EVAL1 code works. At least, up through USB_CoreReset().

 

At startup, the code calls USB_CoreInit() which calls USB_CoreReset(), both in stm32f4xx_ll_usb.c.

From USB_CoreReset():

  /* Core Soft Reset */
  count = 0U;
  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
  do
  {
    if (++count > 200000U)
    {
      return HAL_TIMEOUT;    // <<<--- THIS LINE ALWAYS HIT
    }
  }
  while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
 
  return HAL_OK;

 

Does completion of that reset depend on the 60MHz PHY clock from the USB3300 (USB_OTG_HS_ULPI_CK input to STM32F429) being active?

Any ideas why that clock might not be present? Based on the USB3300 data sheet, it looks like it should be running as long as the part has power, VBUS, and a 24MHz XTAL connected.

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