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CubeMX BUG: Setting LSE Drive Capability

Question asked by Clonimus74 on Oct 17, 2017
Latest reply on Mar 20, 2018 by Jeanne Joly

When using CubeMX, with STM32L476, for setting LSE drive capability other than "Low Drive" the setting will not be implemented. This is due to the fact that the write access using bit DBP in PWR->CR1 is not set prior to setting RCC->BDCR value.

 

The code generated in SystemClock_Config is:

void SystemClock_Config(void)
{

RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInit;

/**Configure LSE Drive Capability
*/
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);

/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
....

}

 

where HAL_PWR_EnableBkUpAccess must be executed prior to __HAL_RCC_LSEDRIVE_CONFIG

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