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How to synchronize timers with offset (delay of half a carrier cycle)?

Question asked by Elijah Toppo on Oct 12, 2017



I am new here. I tried searching for a similar problem in the forums but didn't find anything that matches. So I'm posting my question in a new post.


The question can be best described with an image.

Conceptual diagram of two timers synchronized with offset

I want to use two timers which are synchronized but with a delay of half a period. 

I have written code that synchronizes two timers (TIM1 and TIM8) with TIM2 update events clocking both counters and it works fine. But I am not able to provide the delay of ARR counts. 



1) I tried starting TIM8 with ARR to see if the CenterAligned3 mode would start it as a down counter, but it doesn't.

2) I also tried setting the DIR bit for TIM8 in the CR1 register for downward mode. But then when I start the timer in CenterAligned3 mode it doesn't work. My guess is that one can't write into the DIR bit when choosing mode as centeraligned.



One option I think might work is not setting center aligned mode and on every update interrupt changing the DIR in software. But that would add as software overhead for the code. Also I'm not sure in that case will I get an interrupt when the CCR values match with the CNT register (this is for the other parts of the program).


It would be a great help if you guys could advise me on this issue.

Thank you so much.