I'm looking to use the FMC in Synchronous PSRAM 16-bit mode, and need to run CLKDIV of 3 (or 4). The reference manual (RM0410) waveforms seem to show only a setting of CLKDIV=2. In figure 50/51, CLK is shown toggling every rising HCLK edge. How does it behave when CLKDIV=3?
For example, in figure 50, NADV is low for 2 HCLKs, or 1 CLK period, and AD[15:0] is valid for 2 HCLKS before, and 1 HCLK after NADV rising edge. How does it behave when CLKDIV=3?