AnsweredAssumed Answered

STM32L476 LPTIM1 counter register

Question asked by Juha Aaltonen on Oct 6, 2017
Latest reply on Feb 15, 2018 by Balasubramanian vaidhyanathan

I know the counter register read is not very reliable:

Bits 15:0 CNT: Counter value
When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may
return unreliable values. So in this case it is necessary to perform two consecutive read accesses
and verify that the two returned values are identical.
It should be noted that for a reliable LPTIM_CNT register read access, two consecutive read
accesses must be performed and compared. A read access can be considered reliable when the
values of the two consecutive read accesses are equal.

But how many reads is normal?


I tried to find the "edge" by:


uint32_t read_count()


    uint32_t tmp1, tmp2;

    tmp1 = HAL_LPTIM_ReadCounter(&hlptim1); // hlptim1 is a global variable

    while ((tmp2 = HAL_LPTIM_ReadCounter(&hlptim1)) != tmp1) tmp1 = tmp2;

    return tmp1;



uint32_t poll_count_change()


    uint32_t tmp;

    tmp = read_count();

    while (read_count() == tmp);

    return get_systicks();



the worst case seemed to be that the poll_count_change() took about 45ms!

Is that anywhere near normal?

The LPTIM1 was running on LSE and with prescaler 2 and the processor was running @ 48MHz.