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STM32H743 possible bug, or two :)

Question asked by Oleg Skydan on Sep 22, 2017
Latest reply on Sep 26, 2017 by Oleg Skydan

Hi, All!


I have made a board with STM32H743 (ES32H743 rev.Z datecode 633) and ported quite a big STM32F746 project to STM32H743. The works is not yet finished, but I have some questions and information that can be useful for others, so I want to share it.


DMA2D hangs reading data from the ASIB which actively exchanges data with the other(s) AMIB(s).


Arrange Cortex-M7 core to actively use AXI SRAM or FLASH A (probably other slaves can be used, but were not checked). Arrange DMA2D to read data from the same slave (AXI SRAM or FLASH A). You should see DMA2D hangs in a short time. Debugger shows the START bit in DMA2D CR register remains set, but no flags are set in the DMA2D ISR register, and DMA2D do nothing (requested operation is not executed).


Setting bit 0 (READ_ISS_OVERRIDE) in the AXI_INI5_FN_MOD register completely
solves the above problem:
*((__IO uint32_t*)0x51046108) = 0x1;


There is also another problem with DMA2D. It works finely if the destination is the internal SRAM, but when its destination is the FMC SDRAM it looks like it writes data only in 8bytes chunks aligned to the 8bytes boundary. So the vertical line in the RGB565 frame buffer looks like the line at the right place with some "padding to 4pixels" around it. The result (line+padding) is aligned to 4pixels (8bytes in the frame buffer).


If I draw using the CPU everything is ok, the same DMA2D code works nicely for the internal SRAM and on the STM32F746 processor. The different memory tests (SDRAM) shows no errors. The chip is MT48LC32M16A2 running at 100MHz.


The board is a bit unusual in hardware - the low address byte lines are swapped:

* A0 ------ A4 | A0 ------- A7
* A1 ------ A5 | A1 ------- A6
* A2 ------ A6 | A2 ------- A4
* A3 ------ A7 | A3 ------- A5
* A4 ------ A2 | A4 ------- A0
* A5 ------ A3 | A5 ------- A1
* A6 ------ A1 | A6 ------- A2
* A7 ------ A0 | A7 ------- A3


It should not bring any problems according to manuals, but maybe I have missed something? The SDRAM mode register is programmed with address lines swapping in mind.