I'm using the input capture digital filter function of TIM15 on STM32F070CB. I need to filter out pulses shorter than 1.5ms and I want to keep FCLK at 48MHz.
Problem is, in this case, I can't have a TIM15 timer clock slower than 6MHz (div/16*2), then divided by 4 (max.) with CKD=10, then using fDTS/32 with 8 samples (max.). This gives a period of 170us, which is definitely too short for me.
I tried to use TIM3 as prescaler for TIM15, but it doesn’t seem to work because fDTS is directly taken from fCK_INT (see AN4776), which cannot come from TIM3 (only CK_PSC of TIM15 can come from TIM3).
Any idea of configuration allowing filtering out pulses shorter than 1.5ms while keeping FCLK=48MHz?