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ADC running at half speed

Question asked by Dave Jones on Sep 17, 2017
Latest reply on Sep 19, 2017 by pevy.andy

I am working with an STM32L452 on a custom board. I use System Workbench as my development system. The initialization code is generated by CubeMX. All of those have been updated (today) to the latest versions.


I have the part configured using an internal oscillator and PLL to run at 80MHz. The system clock, bus clocks, and ADC clock are all at 80 MHZ. I am converting 5 channels through the ADC. They are "slow" channels, which according to the reference manual simply means they require a longer sampling time. The data sheet shows them capable of sampling and converting at up to 4.21Msps. I am using a slightly longer sampling time (12.5 cycles instead of the 6.5 cycles minimum required for slow channels). The data sheet shows the conversion is 12.5 cycles, so with 12.5 cycles sample time that adds up to a total of 25 cycles for the sampling and conversion.


With an 80MHZ clock and 25 cycles total conversion time, that means it should take 312ns per channel to convert. With 5 channels converting, that should mean I get back 5 results every 1.562 uSec. I double checked these calculations based on the datasheet saying the slow channels can run at 4.21Msps on an 80 MHz clock. That uses a 6.5 cycle sample time and 12.5 cycle conversion. 80MHz/19 cycles = 4.21Msps. So my math is correct, and I should be converting at 3.2Msps. (and 5 channels at 640Ksps each)


I  have it configured to use DMA and a 10 sample buffer, so I get 5 channels on the half complete interrupt and an updated 5 channels on the fully complete interrupt. I am toggling a GPIO pin in those interrupts and watching it on a scope.


Discontinuous mode is disabled, as are injections.


The actual times between interrupts are measuring at about 3 uSec for the first one and about 3.5 uSec for the second one. That is half the calculated speed I described above. If I change the ADC clock pre-scaler from 1 to 8, those same times are 8 times slower as expected, and still half what the calculated speeds are.


I searched here and the only thing I found was from 2 years ago where somebody pointed out that CubeMX was setting the JAUTO bit even when no injection channels were being used, and that was slowing down the ADC.


[Bug] CubeMX, STM32L4, ADC synchronuous clock settings 


But, I checked that by reading the ADC1->CFGR register during my interrupts, saving it, and at a later time reading the saved value via an external device on a serial port where I could examine the value. The JAUTO bit was not set. Neither were any other bits that seemed suspicious.


So, what is going on here???    Anybody have any ideas??