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STM32F407 SPI RXNE flag bit clears automatically

Question asked by gopi natarajan on Sep 10, 2017
Latest reply on Sep 10, 2017 by Vangelis Fortounas

Hi all, I am using STM32F407 Discovery board and trying to initialize and retrieve the data from the on-board accelerometer. I have properly initialized the PA5, PA6 & PA7 as SCLK, MISO & MOSI pins respectively. The SPI1 is also properly initialized with MSTR, CPOL, CPHA, SSI, SSM & SPE bits set in CR1 and SSOE bit set in CR2 (First, i would like to use polling mode for Data Transmission/Reception). 

After the initialization part gets over, I try to read the FIFO status register of the accelerometer by sending its corresponding address byte following a dummy byte to retrieve the register value and end up with either the Overrun flag bit set in the Status register (SR becomes 0x42 indicating OVERRUN and TXE bits are set) or the data byte is received in the SPI1->DR and the RXNE bit is set, but gets cleared even before the controller tries to read the status register. As a result, my polling condition gets struck in a continuous loop that will never break.

 

Kind note:

1. As this is an example I am trying to build, I skipped to exit the continuous loop by providing some time deviation or performing the SPI Read/Write operation via TXE and RXNE interrupts.

2. Compiler is CooCox CoIDE V1.7.8. with GNU compiler.

3. I verified the RXNE bit gets cleared even when I perform a single step debug.

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