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STM32L4 series PLLs?

Question asked by Juha Aaltonen on Sep 4, 2017
Latest reply on Sep 7, 2017 by Nesrine M

There seems to be something I don't quite get.

In the reference manual it says "The PLLs input frequency must be between 4 and 16 MHz." and "The selected clock source is divided by a programmable factor PLLM from 1 to 8 to provide a clock frequency in the requested input range".

Also all other PLL parameters are described to be dividers.

How do you get 80 MHz?