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Debugging resets - Watchdog resetting even after clearing?

Question asked by Andres Cao on Aug 29, 2017
Latest reply on Sep 18, 2017 by Andres Cao

Hi!

 

I have some very sporadic resets that are proving troublesome to debug. I'm using an STM32L083

 

Based on the RCC_CSR there's an IWDG reset. The IWDG is definitely enabled (total time of 28s) and being cleared often.

 

Do you know of any reasons I could get an IWDG reset, besides a timeout? The RTC is waking the device from sleep up every 10 seconds and clearing the IWDG.

 

I thought that a fault handler (Hal Error_Handler or HardFault_Handler) could be triggered, and enabled console messages in case it ends up there. I never read any of those messages.

 

Is there any other default infinite loop? Any input ideas are welcomed.

 

Thanks!

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