We are using STM32F7 in our project, We have interfaced WiFi chip with STM32F7 on SDMMC2 interface.
We are getting Fifo Error event when performing block data transfer using DMA with low layer driver. As per datasheet this can occur if we get overrun , underrun eror or burst size length mismatch. But we are not getting any overrun or underrun error in SDMMC2_STA register. So, this may occur due to configuration mismatch, but i am not able to find any clue.
Here i have pasted code snippet of SDMMC and DMA configuration.
/* SDIO transfer prepare */
SDIO->DTIMER = (uint32_t) 0xFFFFFFFF;
SDIO->DLEN = dma_transfer_size; // size is 0x400
SDIO->DCTRL = (uint32_t)sdio_get_blocksize_dctrl(block_size) | bus_direction_mapping[(int)direction] | SDIO_TransferMode_Block | SDIO_DPSM_Enable | (1 << 3) | (1 << 11);
/* DMA2 Stream0 */
DMA2_Stream0->CR = 0;
DMA2->LIFCR = (uint32_t) ( 0x3F );//( 0x3F << 22 );
DMA2_Stream0->FCR = (uint32_t) ( 0x00000021 | DMA_FIFOMode_Enable | DMA_FIFOThreshold_Full /*| (1<<7) fifo err */ );
DMA2_Stream0->PAR = (uint32_t) &SDIO->FIFO;
DMA2_Stream0->M0AR = (uint32_t) dma_data_source;
DMA2_Stream0->NDTR = dma_transfer_size/4; //0x100
/* DMA transfer configuration */
DMA2_Stream0->CR = DMA_DIR_MemoryToPeripheral |
DMA_Channel_11 | DMA_PeripheralInc_Disable | DMA_MemoryInc_Enable |
DMA_PeripheralDataSize_Word | DMA_MemoryDataSize_Word |
DMA_Mode_Normal | DMA_Priority_VeryHigh |
DMA_MemoryBurst_INC4 | DMA_PeripheralBurst_INC4 | DMA_SxCR_PFCTRL | DMA_SxCR_EN | DMA_SxCR_TCIE;
After executing above instruction we are getting DMA fifo error event.LISR = 0x00000001;