I'm experiencing strange behavior of QSPI peripheral (or may be flash chip itself -- N25Q128 in SO8; chips are not shiny new, but never used; datasheet Rev. 8 July 2014): despite what is stored in NVCR/VCR registers, number of dummy cycles is 10. Chip is "fresh" from reel, datasheet says that chips are coming with NVCR factory preprogrammed to 15 dummy cycles (0b1111) for maximum compatibility and maximum clock speed (108MHz). I've checked it - yes, NVCR is 0xFFFF (all '1's) as in datasheet, same as VCR.
Quad Command Fast Read (QCFR) has that dummy phase, so I'm writing 0xF to QUADSPI->CCR.DCYC and expecting that i will get my data intact. But instead of this i see that data output is somehow shifted in time for some fixed number of clocks, independent of clock frequency (I've checked this on 108MHz and 1MHz, even with maximum prescaler factor). By using empirical approach I've found that actual number of dummy cycles is not 15, but 10! Strangely enough, datasheet' illustration for Quad Command Fast Read shows 10 dummy cycles.
When i've discovered actual number of DCYCs, i've re-tested code on maximum clock speed and it worked flawlessly - DMA writes, DMA reads, everything looks fine.
So this is my question: how can I pre-determine number of dummy clocks without experimental evaluation? Is this "dummy cycle" same thing in ST and Numonyx documentation? Where I've lost 5 cycles? Is this hardware quirk or just my misunderstanding?