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How to achieve maximum system clock (168MHz) in stm32f446zet

Question asked by ANNU CHERIAN on Aug 18, 2017
Latest reply on Aug 24, 2017 by ANNU CHERIAN

RCC->APB1ENR |= (1<<28);

PWR->CR |= (PWR_CR_VOS);

               

RCC->CR |= (1<<0);

RCC->CR |= (RCC_CR_HSICAL_4);                                   // Internal high-speed clock calibration

RCC->CFGR |= RCC_CFGR_SW_HSI;                              // HSI oscillator selected as system clock

RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;                      // APB high-speed prescaler (APB2)

RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;                      // APB Low speed prescaler (APB1)

RCC->CFGR |= RCC_CFGR_HPRE_DIV1;                        // AHB prescaler

RCC->CR &= ~(1<<24);                                                       //  PLL OFF

RCC->PLLCFGR &= ~(1<<22);                                           // HSI clock selected as PLL

RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLM;        

RCC->PLLCFGR |= RCC_PLLCFGR_PLLM_4;                  // Division factor for the main PLL (PLL) input clock (16)

RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLN;             

RCC->PLLCFGR |= RCC_PLLCFGR_PLLN_4;                  // Main PLL (PLL) multiplication factor for VCO (336)

RCC->PLLCFGR |= RCC_PLLCFGR_PLLN_6;

RCC->PLLCFGR |= RCC_PLLCFGR_PLLN_8;          

RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLP;                

RCC->PLLCFGR |= RCC_PLLCFGR_PLLP_1;                 // Main PLL (PLL) division factor for main system clock(2)

RCC->CR |= (1<<24);                                                         // enable PLL       

while(!(RCC->CR & RCC_CR_PLLRDY));                       // waiting for PLL lock

RCC->CFGR |= RCC_CFGR_SW_PLL;                           // PLL_P selected as system clock

 

Above code shows configuration to achieve maximum system clock (168MHz) , but during running time on keil uvision5 compiler  shows "cannot access memory" . Please suggest a method to solve this issue .......

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