As per the STM32F42xx errata sheet (http://www.st.com/content/ccc/resource/technical/document/errata_sheet/38/e6/37/64/08/38/45/67/DM00068628.pdf/files/DM00068628.pdf/jcr:content/translations/en.DM00068628.pdf) the errata no , "2.11.5 Interruption of CPU read burst access to an end of SDRAM row",this issue is Fixed in the Device Revision 3,4 and B.
As per table 4 mentioned in the errata , the work around of 2.11.5 need not to be applied on device revision 3,4 and B.
But as per our experiments, we are observing this issue https://community.st.com/thread/37200-4-bytes-repeating-when-using-memcpy even on Device Revision 3,4 and B.
At the same time, if we repeated the experiment after applying the work around say Enable the read FIFO by setting the RBURST bit in the FMC_SDCR1 register, the issue https://community.st.com/thread/37200-4-bytes-repeating-when-using-memcpy not observed
Please let us know whether the work around Enable the read FIFO by setting the RBURST bit in the FMC_SDCR1 register is applicable for all device revision such as revision “A”, “Y”, “1”, “3”, “4”, “B”?
Thanks and Regards,
Krishna Prasad M