One nice security feature in the STM32F072 is to have a SRAM parity check.
I am providing you a simple example based on Cube library to enable SRAM parity check in your firmware (instead of enabling it by SWD using a JTAG debugger).
Tip: One important tip is that you need in this case to erase the user option byte where the SRAM parity bit is before programming it otherwise you will receive an programming error.
To run the code you will need to unzip the attached code at:
I ran the code on a STM32F072 Discovery Kit.
Here is more about SRAM parity check in the F072:
The user can enable the parity check using the option bit RAM_PARITY_CHECK in the user option byte:
Bit 22: RAM_PARITY_CHECK
0: RAM parity check enabled
1: RAM parity check disabled
The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in order to increase memory robustness, as required for instance by Class B or SIL norms. The parity bits are computed and stored when writing into the SRAM. Then, they are automatically checked when reading. If one bit fails, an NMI is generated.
The same error can also be linked to the BRK_IN Break input of TIM1/15/16/17, with the SRAM_PARITY_LOCK control bit in the SYSCFG configuration register 2 (SYSCFG_CFGR2). The SRAM Parity Error flag (SRAM_PEF) is available in the SYSCFG configuration register 2 (SYSCFG_CFGR2). Note: When enabling the RAM parity check, it is advised to initialize by software the whole RAM memory at the beginning of the code, to avoid getting parity errors when reading non-initialized locations.
The detection of the Parity SRAM can be output on an IO as explain below:
Usage of Parity bit in SYS registers:
SRAM_PEF: SRAM parity error flag This bit is set by hardware when an SRAM parity error is detected. It is cleared by software by writing ‘1’.
0: No SRAM parity error detected
1: SRAM parity error detected
SRAM_PARITY_LOCK: SRAM parity lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM parity error signal connection to TIM1/15/16/17 Break input. 0: SRAM parity error disconnected from TIM1/15/16/17 Break input
1: SRAM parity error connected to TIM1/15/16/17 Break input
LOCKUP_LOCK: Cortex-M0 LOCKUP bit enable bit This bit is set by software and cleared by a system reset. It can be use to enable and lock the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input.
0: Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input
1: Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input