Quick question about pin and I2S/SAI clock sources.
If I wanted to use I2S_CLK pin (PC9) as kernel clock for I2S and SAI devices what is the recommended frequency in order to meet 44.1K and 48khz, 96Khz and 192Khz sampling? Section 50.9.9 in the technical manual and gives some equations. The CLKGEN as far as I can tell cannot divide down to multiples of 44.1k AND 48.0k. Is that right?
Or do I rely on PLL3 to do a good job for audio?