Hello, i made my own devkits with huge altera and STM32F4/7 micro-controllers.
As usual, STM32F479 performing very well, it uses 26b ADR, 32b data lines directly to FPGA.
But for some reason code generated by STM32CubeMX does not want to work. I mapped 4 banks of SRAM 16Mx32b to SRAM controllers, but they don't work, at all.
I am using this code to test it:
#define Bank1_SRAM1_ADDR ((uint32_t)0x60000000) // FPGA
volatile uint32_t FMC_ADR_R = 0;
volatile uint32_t FMC_ADR_W = 0;
volatile uint32_t FMC_R = 0;
volatile uint32_t FMC_W = 0;
*(uint32_t *) (Bank1_SRAM1_ADDR+FMC_ADR_W*4) = FMC_W;
*(uint32_t *) (Bank1_SRAM1_ADDR+0) = 0;
FMC_R = *(uint32_t *) (Bank1_SRAM1_ADDR+FMC_ADR_R*4);
By using debugger, i am changing FMC_ADR_R, FMC_ADR_W, FMC_W values, and CS goes only single time low during init, after that it keeps high. Adding more delay did not helped between read writes, so i don't know whats hoing on.
Also, in migration documentations i read that it only have single sram controller ( chip select) while STM32F4XX does have 4, whats up to that ? so why CubeMX is very happy generating code for all 4 chip selects ?
Any one knows whats going on ?
My sram init looks like this:
/** Perform the SRAM1 memory initialization sequence
hsram1.Instance = FMC_NORSRAM_DEVICE;
hsram1.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
/* hsram1.Init */
hsram1.Init.NSBank = FMC_NORSRAM_BANK1;
hsram1.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
hsram1.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
hsram1.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_32;
hsram1.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
hsram1.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
hsram1.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
hsram1.Init.WriteOperation = FMC_WRITE_OPERATION_DISABLE;
hsram1.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
hsram1.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
hsram1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
hsram1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ASYNC;
hsram1.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE;
hsram1.Init.PageSize = FMC_PAGE_SIZE_NONE;
/* Timing */
Timing.AddressSetupTime = 5;
Timing.AddressHoldTime = 3;
Timing.DataSetupTime = 5;
Timing.BusTurnAroundDuration = 0;
Timing.CLKDivision = 0;
Timing.DataLatency = 0;
Timing.AccessMode = FMC_ACCESS_MODE_A;
/* ExtTiming */
if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
Also, i was messing with timing, it does not help at all :/