I am a big fan of STM32s and also the CubeMX ecosystem. I like how it's making the initial design flow so easy to use and visually comprehensive.
As I'm also very interested in the advances of FPGAs and SoCs using OpenCL, I thought that this would be a very neat application for ST to look into.
Use a single Cortex-M3 core with decent flash and MINIMUM sram (4K?) and embed that inside an FPGA. The FPGA then creates the link to the package pins.
Use CubeMX and add a new page. That page is like a drawing board and shows the internals of the chip in a graphical way. Then drag&drop SOFT peripheral cores into the chip and wire them up to whichever free GPIO pins you like in any order you like. This can be for example:
- GPIO in the bottom left corner to control pin #1
- an SPI block above that to control pins 3-6 in any order desired
- 5 CAN controllers
- DMA controllers to link them all up
- an FPU or even a 64bit double FPU if required to extend the CPU's instruction set to turn it into an M4 core
- how about a 2nd cpu core? Maybe a small one dedicated for fast control loops?
- SWD debug port
- JTAG debug port
- simply EVERY peripheral
Finally, just tick a box saying "Fill leftover FPGA fabric with SRAM" and a live preview of free SRAM.
Then use HAL just like now to program C/C++.
I think this shouldn't be too hard for ST, as they already have all peripherals as blocks for their different silicon-designs anyway.
So why not split them up and make them easy to use for customers in a way THEY like?
There's so much potential for future expansions on this. You could include OpenCL blocks where customers can write a small kernel and drag&drop the kernel into a new block in CubeMX to build custom peripherals.
This whole SoC idea is so far only available from the big FPGA manufacturers and targeted at HPComputing. Therefore it's REALLY expensive and difficult+complex to get into. I think it should be easy, cheap and simple to do this. And CubeMX with STM32Flex would be my favored approach.
This is how Anandtech said it:
Currently, OpenCL capable FPGAs run into thousands of dollars. This is likely not an issue for the enterprise market typically targeted by FPGA vendors. However, OpenCL on FPGAs has not attracted as much mindshare as GPUs. GPU vendors have a huge advantage that anyone with a cheap laptop can start experimenting with and learning about GPUs. The easy and cheap access to GPUs enabled GPU computing to take off. Whenever computing technology has become cheaper and/or easier to program, it has enabled many creative products around it in fields not thought of by the original technology makers. FPGAs have not yet reached that stage.
ST could be the first to get into that market. And as a bonus, this reduces design-cost for ST as they don't have to maintain 9999 different models of STM32s. Instead, only 4 or 5 with different FPGA sizes.
Let the customers design their own chips!