This line work:
DMA1_Stream7->PAR = (uint32_t)&(DAC->DHR8R1); //Destination DACR1
TIM1 CCR1,2,3,4 verified by simple software counter they are ok.
This line dont work:
DMA1_Stream7->PAR = (uint32_t)&(TIM1->CCR1); //Destination TIM1 CCR1
TIM1 CCR1 destination generates TEIF7 (transfer error flag).
Also strange is that FIFO status (FS) is set to 0x4 (0b100 empty) which suggest
there is no data moved into the FIFO first position which a DMA in direct mode
Can this be a HW bug? Or do i oversee something here? Is this related to the
known F4 FIFO error, if so how to cure it?
Thanks for your time and effort!
/**************** DMA1/Ch3/Stream7 trigged by TIM2 Update Event *****************/
DMA1_Stream7->NDTR = 256; //Number of DMA transfers
DMA1_Stream7->M0AR = (uint32_t)(sine1); //MEM0 source is sine1 table, 8bit res.
DMA1_Stream7->PAR = (uint32_t)&(TIM1->CCR1); //Destination TIM1 CCR1, 8bit res.
DMA1_Stream7->CR |= DMA_CHANNEL_3; //TIM2 UP or TIM2 Ch4 as DMA requests
DMA1_Stream7->CR |= DMA_SxCR_DIR_0; //Read from memory to peripheral
DMA1_Stream7->CR |= DMA_SxCR_MINC; //Memory increment enabled
DMA1_Stream7->CR |= DMA_SxCR_CIRC; //Circular mode enabled
DMA1_Stream7->CR |= DMA_SxCR_PL; //Channel Priority level is Very High
DMA1_Stream7->CR |= DMA_SxCR_EN; //DMA1 stream7 enabled