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CMU - FMPLL clock reference values

Question asked by alem_ on Jul 19, 2017
Latest reply on Aug 9, 2017 by Erwan Y

Hello everyone,

I'm working with SPC56EL60L3 and SPC5Studio v5.0.

I'm not sure I get how does the CMU_0 FMPLL clock monitoring work.

Reading the user manual (RM0032) at page 277 13.3.3 and 13.3.4, I've found some details on the CMU_HFREFR_A and CMU_LFREFR_A registers, but I have some questions.

 

First question: when is the FMPLL clock checked? Whwnever I start the CMU by setting the SFM bit in the CSR register?

 

Second question:

Table 90 says: These bits determine the high reference value for the FMPLL clock. The reference value is given by: (HFREF_A÷16) × (FIRCOSC_CLK÷4). 

 

Table 90 says: These bits determine the low reference value for the FMPLL clock. The reference value is given by: (LFREF_A÷16) × (FIRCOSC_CLK÷4).

 

HFREF and LFREF are the contents of the two register, but what is FIRCOSC_CLK? Is it a predefined value or the content of a register, or what?

Thank you.

 

Regards

Alessandro

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