Aurelien Robert

Routing selection of TQFP or BGA for STM32F7 + SDRAM

Discussion created by Aurelien Robert on Jun 26, 2017
Latest reply on Jul 3, 2017 by Aurelien Robert

I'm making prestudy of a product that should integrate a STM32F767 running at 200MHz, 16 bits SDRAM (for example IS4216160), RGB TFT display (RGB565), ethernet (RMII), sdmmc (4 bits), quadspi...
I will require either the TQFP208 or the BGA2016 pins case because I really need for a lot of pins for all of that.
I'm questionning myself (and you :) about the right choice of cases. I never routed such high speed synchronous wide bus, and never used BGA. But this is not really the problem, I think I can deal with it.

Main issue come from the STM32 to SDRAM connection.
The TQFP case is 30x30mm, that's huge, and the TSSOP SDRAM 22x11mm.
The BGA case for STM32 is 13x13mm, and 8x8mm for SDRAM.
Higher density of BGA means that pin distance on device is short and may reduce the difficulty to route signals at approx same length (+/-10mm according to STM32 app note).
But TQFP and TSSOP have advantages that I can solder myself all the devices, reducing the prototype manufacturing cost and delay, and ease debugging of signals with scope. Moreover, the power dissipation of the TQFP case is better than the BGA case.
On TQFP package, the FMC pins are splitted all around the device, so it will require potentially serpentines of a lot of signals (referring to the SDCLK clock that must be retain straight). I have discarded the idea of placing the SDRAM on the bottom face behind the CPU to reduce power interference during SDRAM refreshes, and ease decoupling.
According to the picture attached showing the FMC signals distribution over the TQFP package, should the best idea to place the SDRAM on the LEFT ? That ensure that the SDCLK signal can remain straight and I can play with serpentines with others signals ? If I place the SDRAM on the right, the clock will be shorter than all other signals and it is not recommended to use serpentines on clock. I can also place the SDRAM on the TOP, that should limit the number of traces that may be delayed (mainly the signals on the top edge of TQFP). Of course final selection will be done with net placement on layout with both devices.

The ethernet, sdmmc, quadspi signals can be regrouped on same side or at least at a close chip location, and run at a lower frequency anyway.
I'm not limited in number of layers, I target 6 layers boards but if 8 layers board is recommended, I will use it

Do you have advices or opinions on that question, from your experience ?