I am experiencing some issues with the ADC on my L0. I configure it with PCLK as the input clock in CKMODE, start it up, and take a sample. Everything works fine. I then decide to set the oversampling mode (which is in the same register as the CKMODE bits) after the ADC has started, but the CKMODE bits get cleared and the ADC does not sample (EOC never happens). This clearing happens no matter what value I write to the register, including 0, the previous value of the CKMODE bits, or the previous value of the entire register. It seems that though the datasheet says the oversample configuration can be changed as long as ADSTART=0 (which is true), any write to the register is unsafe. Am I doing something wrong?
Attached is my code.