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Interruption of CPU read burst access to an end of SDRAM row

Question asked by Krishna M on Jun 20, 2017
Latest reply on Jul 14, 2017 by Krishna M
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We find the following silicon limitation as per section 2.11.15 of STM32F42xx and STM32F43xx Errata Sheet (April 2017 DocID023833 Rev 11). Our queries are appended further below.
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2.11.15 SDRAM bank address corruption upon an interruption of CPU read burst access
Description
If an interrupt occurs during an CPU AHB burst read access to one SDRAM internal bank followed by a second read to another SDRAM internal bank, it may result in wrong data read if all the conditions below are met:
• SDRAM read FIFO enabled. RBURST bit is set in the FMC_SDCR1 register
• An interrupt occurs while CPU is performing an AHB incrementing bursts read access of unspecified length (using LDM = Load Multiple instruction) to one SDRAM internal bank and followed by another CPU read access to another SDRAM internal bank.
The issue occurs only when the address of the second data read access in the following bank match one of the data address in the read FIFO.
Our queries:
1. What happens if an interrupt occurs during an CPU AHB burst read access to one SDRAM internal bank, and a different SDRAM bank is read from within the interrupt? Will the issue be applicable here? If the issue is applicable, would a write to a dummy SDRAM location in some arbitrary bank at the beginning of the interrupt service routine be a safe work around?
2. Is the issue valid for burst and not burst types of read for the "second read to another SDRAM internal bank"  ?
3. Should we take care of any thing else if there are nested interrupts and there is a chance of burst reads to different banks being interrupted in a nested manner? i.e., say the following occurs:
interrupt-1 interrupts a burst read to SDRAM bank-1 and 
in interrupt-1 service routine a burst read to SDRAM bank-2 is interrupted by interrupt-2 and
in interrupt-2 service routine a burst read to SDRAM bank-3 is performed and finally it returns to interrupt-1 service routine and then back to non-interrupt level
4. If we do a dummy write to some fixed SDRAM location after all burst reads that are followed by a read to another SDRAM bank in all interruptible contexts (including lower priority interrupt routines), can we be assured that there will be no corrupted data durung SDRAM read?
5. If consequtive burst reads from a particular SDRAM bank is of size greater than the SDRAM read FIFO (all different addresses), can we be sure that there will be no data in the SDRAM read FIFO that is from a different bank, and thereby the subsequent read to a different SDRAM bank will not be corrupted?
NOTE: The workaround to "disable the SDRAM read FIFO" cannot be used in our project as our SDRAM uses a 16-bit data interface and due to errata clause 2.11.5 titled "Interruption of CPU read burst access to an end of SDRAM row", as a workaround we are forced to enable SDRAM read FIFO.
Regards,
Krishna Prasad M

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