Two problems that I have identified in the L4 HAL code that you should probably be interested in....
Firstly in the SPI FIFO Flush code:
The FIFO can operate in 8 or 16 bit mode, but the 2 bits that are used to track the number of bytes stored in the FIFO can get out of step with the actual content, if the FIFO is set to 16 bit mode.
This means that when you next get data on the channel, it reads out data that was left over from a previous transfer before the new data.
To fix this I have had to force the relevant interface into 8 bit mode before doing the flush.
* @brief Flush the RX fifo.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
HAL_StatusTypeDef PPT_HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
__IO uint32_t tmpreg;
uint8_t count = 0;
/* set fifo rx thresold according the reception data length: 8 bit */
while((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY)
tmpreg = hspi->Instance->DR;
UNUSED(tmpreg); /* To avoid GCC warning */
if(count == SPI_FIFO_SIZE)
Next, to make the RTC issue a wakeup interrupt the wakeup timer (RTC_FLAG_WUTF) flag must be cleared when enabling the RTC.
If this is not done, the wakeup happens but no interrupt is generated.
void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
/* Peripheral clock enable */
/* Peripheral interrupt init*/
HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 5, 0);
// Need this here until Cube is fixed. [AP] [BUGFIX]