AnsweredAssumed Answered

STM32L4 FMC Latched SRAM

Question asked by Gabriel Roux on Jun 9, 2017
Latest reply on Jun 23, 2017 by Gabriel Roux

Hi All,

 

I am currently working on migrating a system from a EFM32 ARM Cortex-M3 to the STM32L476VGT ARM Cortex-M4. In the current hardware implementation, the processor is connected to asynchronous SRAM via an FPGA  that acts as an address latch (among other things). The following is an excerpt from the EBI (The external memory controller on the EFM32 Gecko chips) application notes explaining the workings of the current SRAM hardware connection.

 

"The data bus width of the EFM32 EBI is 16 bits. When multiplexing the address and data bus, these 16 signal lines are first used for putting out the least significant 16 bits of the address, which are then held by the external address latch. Then these 16 signal lines are either used for 16 bits of data, or 8 bits of data and the remaining 8 bits of the address. See Figure 2.1 (p. 5) for an overview of the signals and address latch needed for multiplexed operation. The rest of the control signals are the same as in the non-multiplexed operation example" (Figure 2.1 is attached)

 

Control signals used are Read Enable, Write Enable and Address Latch Enable. 1MBs data is read in, in 8 bit mode.

 

Would it be possible to implement this asynchronous, latched SRAM by using the STM32L476VGTs FMC in multiplexed mode?Also, from the reference manual I can't determine whether or not SRAM can be used in multiplexed mode on this chip, it seems that the FMC only allows that for PSRAM?

 

I noticed that pin A17 can be used as an ALE pin in the case of NAND flash memory, is it per chance possible to use this as an ALE pin for controlling SRAM as well?

 

Any help would be greatly appreciated!

Attachments

Outcomes