AnsweredAssumed Answered

STM32F3 IWDG strange behaviour

Question asked by ott.simon on Jun 5, 2017

I have implemented the IWDG on the STM32F4 and it works without problems. I have the DBG_IWDG_STOP bit in the  DBGMCU_APB1_FZ set to avoid Watchdog Faults i.e. when debugging. 


Did I get it right that the watchdog in all of the following situations: Power is shut down, Microcontroller is flashed, Watchdog has occured? And then has to be enabled again in the software. At least this seems to be the case with the STM32F4. 


I now tried to implement the IWDG on the STM32F302K8U. In the main(), the controller waits for some time, then the IWDG is enabled and then the RTOS starts where the IWDG is reloaded regularly. However, the controller seems to reset all the time. If I turn off the delay, the controller runs. So for me it seems, as if the IWDG is active right from the start after flashing/booting, which is not intended. 


Is this normal? 


(Just in case that this has anything to do with it: Another strange thing I recognized is, that I get the message "Warning: CPU is running at low speed (8100 kHz)" when starting to debug/flash. However, the CPU has to be running at the correct speed as CAN/USART/Timers are all working fine). Also when starting to debug, often it fails to halt at the start of main which is the normal behaviour with the STM32F4. I then have to reset to be able to properly debug.) 


In the main I have the following code: 


if (RCC_GetFlagStatus(RCC_FLAG_IWDGRST)== SET)


   // Indicate that a watchdog fault has occured previously


   // Reset flag  




// Configure IWDG to freeze if the controller is stopped



// Configure the timeout. 




After that, regularly IWDG_ReloadCounter() is called. 


(I tried to format the source code with that button but it didn't work...the new forum style is pretty confusing, sorry for that)