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Regarding the state of CPU while DMA controller access bus for Data transaction.

Question asked by gaurav kumar on Jun 3, 2017


Is CPU halt when DMA access the bus for data transfer between peripheral and memory? if it is true then why in Application note  AN4031 they have written


''The DMA allows data transfers to take place in the background, without the intervention of
the Cortex-Mx processor. During this operation, the main processor can execute other tasks
and it is only interrupted when a whole data block is available for processing."


because if CPU halts, then it doesn't matter whether CPU resources are free or not...