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SPC56EL60L3- flash array integrity check

Question asked by alem_ on May 22, 2017
Latest reply on Jun 14, 2017 by Mosè Pernice

Hello, I'm working with SPC56EL60L3 and SPC5STUDIO v5.0.

I need to implement flash array integrity check,as part of the power on self test procedure.

I got some sample code from ST application engineering, but I can't get it to work.

The odd thing is that, if I try to run the code in debug mode, it works.. When I try to run it outside of the debig mode, I get an unhandled exception.

 

Please find my code below (I made some little changes to the code provided by ST application engineer).


/* flash array integrity test */
#define PAR_CFLASH_MISR0 0xBFC5FC60
#define PAR_CFLASH_MISR1 0x2D32A870
#define PAR_CFLASH_MISR2 0xDAF09F36
#define PAR_CFLASH_MISR3 0xC0DB86FF
#define PAR_CFLASH_MISR4 0x00016014

#define FLASH_PSW 0xF9F99999

#define UT0_UTE 0x80000000U
#define UT0_AID 0x00000001U
#define UT0_AIE 0x00000002U
#define UT0_AIS 0x00000004U


static int32_t CoreFlashIntegrityTest( void )
{
int32_t retVal_i32 = CORE_TEST_ERROR;
int8_t misrErrCounter_i8 = 0;

CFLASH.UT0.R = FLASH_PSW;

while( ( CFLASH.UT0.R & UT0_UTE ) == 0);

CFLASH.HBS.R = 0x000003FF;
CFLASH.UT0.R &= ~( UT0_AIS ); /* Default value is zero*/

/* Seed the MISR UM0 thru UM4 with desired values.*/
CFLASH.UMISR[0].R = 0U;
CFLASH.UMISR[1].R = 0U;
CFLASH.UMISR[2].R = 0U;
CFLASH.UMISR[3].R = 0U;
CFLASH.UMISR[4].R = 0U;

/* Array Integrity Enable */
CFLASH.UT0.R |= UT0_AIE;

while( ( CFLASH.UT0.R & UT0_AID ) == 0 );

misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[0].R, PAR_CFLASH_MISR0 );
misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[1].R, PAR_CFLASH_MISR1 );
misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[2].R, PAR_CFLASH_MISR2 );
misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[3].R, PAR_CFLASH_MISR3 );
misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[4].R, PAR_CFLASH_MISR4 );

CFLASH.UT0.R &= ~( UT0_AIE );

if ( misrErrCounter_i8 == 0 )
{
retVal_i32 = CORE_TEST_OK;
}

return retVal_i32;
}

Furthermore I have the following questions:

- HBS setting: how do I configure HBS. It looks like it's used for selecting the flash sectors on which I want to run the test. How do I relate the desired sector to the register value?
- In the sample code the MISR[0:4[ registers are initialized to 0. Why is that? Is 0, always the right value?
- In the sample code, the MISR[0:4] registers are compared to some expected values at the end of the test. How do I determine the expected values? Are those fixed values?


Thank you.
Regards
Alessandro

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