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External interrupt flags latching behaviour?

Question asked by marton.miklos on May 10, 2017
Latest reply on May 8, 2018 by Pavan Kumar Ogirala

I am working on a code which utilizes External interrupts on the PORT B.

STM8AF5286 is used with the Cosmic compiler.


I have not found any information about how the interrupt flags are handled internally and knowing their behavior would be important for my project.


On the logic analyzer capture below you can see that the pulse on the PORTB 0 is 1.26 us, which triggers two interrupts. which first and last instruction toggles the pin captured with the ISR channel.


The PB_ODR read is performed in the next instruction after the ISR pin low to high transition. 

In both routines it reads zero from the PORT B.


Is there any way to clear the pending interrupt flag in the serviced interrupt routine?