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STM32F1xx SCB::ICSR::VECTACTIVE field - R/W or RO?

Question asked by Space.Anton on May 4, 2017

Hi there. According to PM0056 (4.4.3) VECTACTIVE field of ICSR register has read-write access. But in ARM DUI 0552A (4.3.3) this field marked as read-only. The latter looks more logical, because the rest of ICSR ignores writes of 0, so PENDSVSET, PENDSVCLR, PENDSTSET, PENDSTCLR bits can be set by writing of 1 at corresponding bit position and zeros elsewhere. If VECTACTIVE field has RW access (as mentioned at PM0056), then this logic turns to be broken and one have to perform read-modify-write access to ICSR. Thus, there is a question. Is there an error in PM0056 (4.4.3), or does ICSR behaviour intentionally differ from specified in ARM docs?

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