The problem appears on CAN2 (don't know yet if it appears on CAN1 or CAN3).
I'm using HAL_CAN_Transmit_IT() to send data.
In the CAN2_TX_IRQHandler() I call HAL_CAN_IRQHandler().
1. Send 1 CAN frame on mailbox0.
1. When the TX Interrupt is entered, the CAN_TSR register doesn't show the flags: RQCP0 and TME0 as beeing set.
2. The RQCP0 and TME0 flags are set, but it seems with a pretty high delay from executing the TX Interrupt.
3. The documentation "RM0410 -> STM32F76xxx and STM32F77xxx" specifies that the TX Interrupt is triggered when flags: RQCPx is set while TMEIE bit is enabled.
1. Question: How does the CAN TX Interrupt gets triggered without RQCPx set in the CAN_TSR?
1. Send one CAN frame and check the CAN_TSR for available mailboxes, after exiting the TX Interrupt.
I found the following pattern of free mailboxes:
(each number represents tx free mailbox that is going to be used for sending the frame)
0000101010101 | 0000101010101 | 0000101010101 | 0000101010101