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EXTI minimal pulse length clarification

Question asked by waclawek.jan on Apr 25, 2017
Latest reply on Jul 10, 2017 by waclawek.jan

DS STM32F405xx STM32F407xx, DocID022152 Rev 8, Table 50. I/O AC characteristics :

tEXTIpw Pulse width of external signals detected by the EXTI controller  - min.10ns

This hints that there's a pair of edge-sensitive latches for each EXTI input, independent from any internal clock.

 

RM0090, DocID018909 Rev 13, 12.2.1  EXTI main features says otherwise:

The main features of the EXTI controller are the following:

[...]

detection of external signals with a pulse width lower than the APB2 clock period. Refer
to the electrical characteristics section of the STM32F4xx datasheets for details on this
parameter.

 

Max. APB2 clock is 84MHz so the period is >10ns; but regardless, the DS should not use a fixed value if it is APB-clock dependent.

 

ST, please clarify.

 

JW

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