AnsweredAssumed Answered

SPI configuration - Send & Receive

Question asked by 123.abc on Apr 21, 2017
Latest reply on May 2, 2017 by Erwan Y

Hi, I am trying to configure the SPI module on the SPC570S40E1 microcontroller to communicate with an external device.

 

The device requires message length of 40 bits.I would like to know if I am setting up the function for exchanging data correctly. The issue I am seeing currently is right after pushing the set of frames( 16,16, 8 bits) to transfer the second message, the EOQF and the TXRXs bits in the status registers remain set even after clearing the EOQF bit. You can see the the second time I am calling the Transmit_DSPI0 in the DSPI_0_Exchange function in the code below.

 

Here is the source code.

 

// SPI driver

#include "SPI.h"
#include "STM.h"


void Initialize_DSPI0(void)
{

     // Configure DSPI0 Module Configuration Register ( DSPI0_MCR )
          // MSTR           - 1      , Master mode
          // CONT_SCKE     - 0      , Continuous SCK disabled
          // DCONF          - 00     , SPI
          // FRZ               - 0          , Do not halt serial transfers in debug mode
          // MTFE               - 0          , Modified Timing Format disabled
          // ROOE               - 0     , (Receive FIFO Overflow Overwrite) Incoming data is ignored
         // PCSIS0          - 1      , Inactive state of PCS0 is high
          // MDIS               - 1          , Allow external logic to disable DSPI clocks
          // DIS_TXF          - 0      , TX FIFO enabled
          // DIS_RXF          - 0     , RX FIFO enabled
          // XSPI               - 0          , Normal SPI Mode
          // FCPCS          - 1     , Fast Continuous PCS mode.
          // PES               - 0          , SPI frame transmission continues
          // HALT               - 0      , Start transfers
     DSPI_0.MCR.= 0x80010004;

     // Configure CTAR0 and CTAR1 ( Clock and Transfer Attributes ) Register
          // Two transfer attributes used. CTAR0 configured for 16-bit frame size. CTAR1 configured for 8-bit frame size.
          // DBR                    - 0          , Baud rate not doubled
          // FMSZ(for CTAR0)  - 1111  , Frame size set to FMSZ + 1 or 16 bits
          // CPOL                    - 0          , Clock Polarity - Inactive state value of SCK is low
          // CPHA                    - 0          , Data is captured on the leading edge of SCK and changed on the following edge
          // LSBFE               - 0      , MSB is transferred first
          // PCSSCK               - 00     , PCS to SCK Prescaler value is 1
          // PASC                    - 00     , Sets the delay between last SCK edge to negation of CS, 00 sets the Prescaler value to 1
          // PDT                    - 00     , Sets the delay between negation of PCS at end of frame to assertion beginning of next frame, 00 - Prescaler set to 1
          // PBR                    - 00      , Baud Rate Prescaler, set to 2. Available values - 2,3,5, and 7
          // CSSCK               - 0000      , PCS to SCK Delay Scaler set to 2
          // ASC                    - 0000     , Scaler value for the After SCK Delay, set to 2
          // DT                    - 0000     , Scaler value set to 2
          // BR                    - 0011     , Baud Rate scaler set to 8

          /* ------------     Calculation ------------------------


             SPI Baud Rate      =  (Fp / PBR) * ( [1 + DBR]/BR )   , Fp = Peripheral Clock / AC0_DC3 = 64/1 = 64Mhz
                                     =  (64/2)       * ( [1]/8 )
                                     =  64/16
                                     =  4Mhz
                                                 

          */

      DSPI_0.CTAR[0].R = 0x78000003;
      DSPI_0.CTAR[1].R = 0x38000003;


}

void Transmit_DSPI0(uint8_t Tx_Frame[])
{


     // Clear transmit FIFO
     DSPI_0.MCR.B.CLR_TXF = 1;


     DSPI_0.PUSHR.R = CONT_Enable  | CTAS(0) | EOQ_Not_Last_Data | Clear_Transfer_Counter | PCS0 | TX_Data(((Tx_Frame[0]<<8)|Tx_Frame[1]));
     DSPI_0.PUSHR.R = CONT_Enable  | CTAS(0) | EOQ_Not_Last_Data | PCS0 | TX_Data(((Tx_Frame[2]<<8)|Tx_Frame[3]));
     DSPI_0.PUSHR.R = CONT_Disable | CTAS(1) | EOQ_Last_Data     | PCS0 | TX_Data(Tx_Frame[4]);

     // Wait until all three frames have been transmitted.
     while (DSPI_0.TCR.B.SPI_TCNT !=  3 )
     {

     }


     //Clear the EOQF bit
     DSPI_0.SR.R = EOQF;

     //wait for the End of Queue flag bit to reset.
     while((DSPI_0.SR.R & EOQF) != 0)
     {

     }

}




void DSPI_0_Exchange(uint8_t Tx_Frame[])
{

     uint8_t Dummy_Message[5] = {0,0,0,0,0};

     // Send the valid frame
     Transmit_DSPI0(Tx_Frame);

     DSPI_0.POPR;
     DSPI_0.POPR;
     DSPI_0.POPR;
     DSPI_0.SR.R = RFDF;

     // Delay 1ms
     Delay_Microseconds(1000);

     // Send a dummy frame to get the response frame
     Transmit_DSPI0(Dummy_Message);

     DSPI_0.POPR;
     DSPI_0.POPR;
     DSPI_0.POPR;
     DSPI_0.SR.R = RFDF;


}









Outcomes