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STM32L4 DMA latency for ADC to SRAM transfer

Question asked by Vogel.Markus on Apr 7, 2017
Latest reply on Apr 7, 2017 by waclawek.jan

Hello everybody,

I have the following situation:

  • Processor STM32L476
  • 48MHz HSE
  • I want to sample an external signal at 4MSPS. Therefore I use 60MHz PLLSAI1 as ADC1's clock
  • This gives 4MSPS (with 2.5cycles sampling and 12.5 cycles conversion - 12bit resolution)
  • ADC1 runs in asynchronous mode and shall sample 4096 points
  • Data are transferred by DMA1, Channel1 to internal SRAM


My question now is:

  • I want to minimize the HCLK to save power
  • So what is the minimal HCLK such that the DMA transfer would still work, i.e. how long does the DMA transfer ADC1 to SRAM take?


What I found out so far:

  • Transfer seems to work when HCLK/(ADC sampling clock) >6 (ADC sampling clock is 4MHz for my 4MSPS), so e.g. I found it works for 24MHz HCLK and 3.73MSPS (ratio is 6.42), works sometimes for 24MHz HCLK and 4MSPS (ratio is 6), never works for 24MHz HCLK and 4.27MSPS (ratio is 5.63)
  • For other processors I found application nodes AN4031 which give delays of 9 AHB cycles, but I guess I found better results for STM32L476, so I don't think these values fit there