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STM32F429ZI Keil v5 and STLink Debugger Access Corrupting While Debugging

Question asked by kasapoglu.orkun on Apr 6, 2017
Latest reply on Apr 10, 2017 by kasapoglu.orkun

Hello. I'm trying to debug our board. It has two SDRAMs which are connected to FMC_Bank5_6 (FMC_Bank1_SDRAM : 0xC0000000 and FMC_Bank2_SDRAM : 0xD0000000). I can debug it a while or step by step again a while but somewhere in debug session it is corrupting and Keil is giving an error which is "Debugger - Cortex-M Error : Cannot access target. Shutting down the debug session.". But code running correctly on the board, test is passed everytime. I'm using STM32F429 SPL v1.3.0 not HAL. I'm not using the SWD pins for any other purpose. They are just what they are in reset and there is nothing about them in the code. It make no sense to me. Because I'm just trying to access 8-bit width to SDRAM and the loop is starting at FMC bank address and end with FMC_BankX_SDRAM + 0x4000000. The error picture attached. Initialization and test code is almost same as the FMC SDRAM peripheral example for STM32F429I-Discovery I'm not using stm32f429i_discovery_xxxxx drivers. I'm just using 8-bit section not both 16- and 8-bit. I've just changed the Row and Column bit width and Refresh Count because I'm using IS42S16320F-7TL. Is it about SPL version or about IDE problem I don't know.

 

EDIT: I have discovered something new about error. Here are the codes for initialization;

 

const uint32_t BANK_ADDR[2] = {FMC_Bank1_SDRAM, FMC_Bank2_SDRAM};
const uint32_t BASE_ADDR[2] = {SDRAM_BANK1_ADDR, SDRAM_BANK2_ADDR};

 

void SDRAM_Init(void)
{
  __IO FMC_SDRAMInitTypeDef FMCSDRAM;
  __IO FMC_SDRAMTimingInitTypeDef Timing;
  int i;
 
  /* Configure the GPIO for FMC SDRAM bank */
  SDRAM_GPIOInit();

  /* Enable FMC clock */
  RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);

 if (TimingDelay_Init(100))
 {
   while(1);
 }

 for (i = 0; i < 2; i++) // Here is different from discovery kit
 {
    /* FMC Configuration -----------------------------------------------------*/
    /* FMC SDRAM Bank Configuration ------------------------------------------*/
    /* Timing configuration for 90 MHz of SD clock frequency (180 MHz / 2) */
    /* TMRD: 2 Clock cycles */
    Timing.FMC_LoadToActiveDelay           = 4;
    /* TXSR: min = 70 ns (7 x 11.11 ns) */
    Timing.FMC_ExitSelfRefreshDelay        = 7;
    /* TRAS: min = 42 ns  (4 x 11.11 ns) max = 120 k (ns) */
    Timing.FMC_SelfRefreshTime             = 4;
    /* TRC: min = 70 ns (7 x 11.11 ns) */
    Timing.FMC_RowCycleDelay               = 7;
    /* TWR: min 1 + 7 ns (1 + 1 x 11.11 ns) */
    Timing.FMC_WriteRecoveryTime           = 2;
    /* TRP: 20 ns => 2 x 11.11 ns */
    Timing.FMC_RPDelay                     = 2;
    /* TRCD: 20 ns => 2 x 11.11 ns */
    Timing.FMC_RCDDelay                    = 2;
 
    /* FMC SDRAM Control configuration ---------------------------------------*/
    FMCSDRAM.FMC_Bank = BANK_ADDR[i];

#if defined(SDRAM_IS42S16400J) // Here is different from Discovery kit
{
    /* Row addressing [7:0] - IS42S16400J */
    FMCSDRAM.FMC_ColumnBitsNumber   = FMC_ColumnBits_Number_8b;
    /* Column addressing [11:0] - IS42S16400J */
    FMCSDRAM.FMC_RowBitsNumber      = FMC_RowBits_Number_12b;
}
#elif defined(SDRAM_IS42S16320F)
{
    /* Row addressing [9:0] - IS42S16320F */
    FMCSDRAM.FMC_ColumnBitsNumber   = FMC_ColumnBits_Number_10b;
    /* Column addressing [12:0] - IS42S16320F */
    FMCSDRAM.FMC_RowBitsNumber      = FMC_RowBits_Number_13b;
}
#endif

    FMCSDRAM.FMC_SDMemoryDataWidth  = SDRAM_MEMORY_WIDTH;
    FMCSDRAM.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
    FMCSDRAM.FMC_CASLatency         = SDRAM_CAS_LATENCY;
    FMCSDRAM.FMC_WriteProtection    = FMC_Write_Protection_Disable;
    FMCSDRAM.FMC_SDClockPeriod      = SDRAM_CLK_PERIOD;
    FMCSDRAM.FMC_ReadBurst          = SDRAM_READBURST;
    FMCSDRAM.FMC_ReadPipeDelay      = FMC_ReadPipe_Delay_1;
    // STDR1 = 0x01116363
    FMCSDRAM.FMC_SDRAMTimingStruct  = (FMC_SDRAMTimingInitTypeDef *)&Timing;
 
    /* Initialization of FMC SDRAM Bank-1 */
    FMC_SDRAMInit((FMC_SDRAMInitTypeDef *)&FMCSDRAM);
 
//    FMC_Bank5_6->SDTR[i] = 0x01116363;
 
    /*  FMC_SDRAM device initialization sequence */
    SDRAM_InitSequence(FMC_Command_Target_bank1 >> i, BANK_ADDR[i]);
 
    /* Configure the GPIO for FMC SDRAM bank (again) */
    SDRAM_GPIOInit();
  }
}

 

/*
+------------------------------------------------------------------------------+
|                             SDRAM Pins Assignment                            |
+------------------+-------------------+-------------------+-------------------+
| PD0  <-> FMC_D2  | PE0  <-> FMC_NBL0 | PF0  <-> FMC_A0   | PG0  <-> FMC_A10  |
| PD1  <-> FMC_D3  | PE1  <-> FMC_NBL1 | PF1  <-> FMC_A1   | PG1  <-> FMC_A11  |
| PD8  <-> FMC_D13 | PE7  <-> FMC_D4   | PF2  <-> FMC_A2   | PG4  <-> FMC_BA0  |
| PD9  <-> FMC_D14 | PE8  <-> FMC_D5   | PF3  <-> FMC_A3   | PG5  <-> FMC_BA1  |
| PD10 <-> FMC_D15 | PE9  <-> FMC_D6   | PF4  <-> FMC_A4   | PG8  <-> FMC_SDCLK|
| PD14 <-> FMC_D0  | PE10 <-> FMC_D7   | PF5  <-> FMC_A5   | PG15 <-> FMC_NCAS |
| PD15 <-> FMC_D1  | PE11 <-> FMC_D8   | PF11 <-> FMC_NRAS |-------------------+
+------------------| PE12 <-> FMC_D9   | PF12 <-> FMC_A6   |
                   | PE13 <-> FMC_D10  | PF13 <-> FMC_A7   |
                   | PE14 <-> FMC_D11  | PF14 <-> FMC_A8   |
                   | PE15 <-> FMC_D12  | PF15 <-> FMC_A9   |

 

Below is different from discovery kit


               +-------------------+-------------------+
               |          PB5  <-> FMC_SDCKE1          | -> SDRAM_U2
               |          PB6  <-> FMC_SDNE1           | -> SDRAM_U2
               |          PC3  <-> FMC_SDCKE0          | -> SDRAM_U1
               |          PC2  <-> FMC_SDNE0           | -> SDRAM_U1
               |          PC0  <-> FMC_SDNWE           | -> COMMON
               +---------------------------------------+
  * ****************************************************************************
  */

static void SDRAM_GPIOInit(void)
{
  GPIO_InitTypeDef gpio;

  /* Enable all gpio port clocks */
  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC |
                         RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE |
                   RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOG, ENABLE);

  /* Common GPIO configuration */
  gpio.GPIO_Mode  = GPIO_Mode_AF;
  gpio.GPIO_Speed = GPIO_Speed_50MHz;
  gpio.GPIO_OType = GPIO_OType_PP;
  gpio.GPIO_PuPd  = GPIO_PuPd_NOPULL;

  /* GPIOB Configuration */
  GPIO_PinAFConfig(GPIOB, GPIO_PinSource5, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_FMC);

  gpio.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6;
  GPIO_Init(GPIOB, &gpio);

  /* GPIOC Configuration  - Here pin2 and pin3 added more from discovery kit */
  GPIO_PinAFConfig(GPIOC, GPIO_PinSource0, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOC, GPIO_PinSource2, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOC, GPIO_PinSource3, GPIO_AF_FMC);

  gpio.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_3;
  GPIO_Init(GPIOC, &gpio);

  /* GPIOD Configuration */
  GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC);

  gpio.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1  | GPIO_Pin_8  |
                  GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
              GPIO_Pin_15;
  GPIO_Init(GPIOD, &gpio);

  /* GPIOE Configuration */
  GPIO_PinAFConfig(GPIOE, GPIO_PinSource0, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOE, GPIO_PinSource1, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOE, GPIO_PinSource7, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOE, GPIO_PinSource8, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOE, GPIO_PinSource9, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOE, GPIO_PinSource10, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOE, GPIO_PinSource11, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOE, GPIO_PinSource12, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOE, GPIO_PinSource13, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOE, GPIO_PinSource14, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOE, GPIO_PinSource15, GPIO_AF_FMC);

  gpio.GPIO_Pin = GPIO_Pin_0  | GPIO_Pin_1  | GPIO_Pin_7  |
                  GPIO_Pin_8  | GPIO_Pin_9  | GPIO_Pin_10 |
              GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
              GPIO_Pin_14 | GPIO_Pin_15;
  GPIO_Init(GPIOE, &gpio);

  /* GPIOF Configuration */
  GPIO_PinAFConfig(GPIOF, GPIO_PinSource0, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOF, GPIO_PinSource1, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOF, GPIO_PinSource2, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOF, GPIO_PinSource3, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOF, GPIO_PinSource4, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOF, GPIO_PinSource5, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOF, GPIO_PinSource11, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOF, GPIO_PinSource12, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOF, GPIO_PinSource13, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOF, GPIO_PinSource14, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOF, GPIO_PinSource15, GPIO_AF_FMC);

  gpio.GPIO_Pin = GPIO_Pin_0  | GPIO_Pin_1  | GPIO_Pin_2  |
                  GPIO_Pin_3  | GPIO_Pin_4  | GPIO_Pin_5  |
              GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
              GPIO_Pin_14 | GPIO_Pin_15;
  GPIO_Init(GPIOF, &gpio);

  /* GPIOG Configuration */
  GPIO_PinAFConfig(GPIOG, GPIO_PinSource0, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOG, GPIO_PinSource1, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOG, GPIO_PinSource8, GPIO_AF_FMC);
  GPIO_PinAFConfig(GPIOG, GPIO_PinSource15, GPIO_AF_FMC);

  gpio.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_15;
  GPIO_Init(GPIOG, &gpio);
}

 

Function is taking the FMC_Bankx_SDRAM as fmc_bank

FMC_Target_bank_x as target_bank

 

static void SDRAM_InitSequence(uint32_t target_bank, uint32_t fmc_bank)
{
  FMC_SDRAMCommandTypeDef sdCMD;
  uint32_t tempr = 0;

  /* Step 3 ------------------------------------------------------------------*/
  /* Configure the clock configuration enable command */
  sdCMD.FMC_CommandMode            = FMC_Command_Mode_CLK_Enabled;
  sdCMD.FMC_CommandTarget          = target_bank;
  sdCMD.FMC_AutoRefreshNumber      = 1;
  sdCMD.FMC_ModeRegisterDefinition = 0;

  /* Wait until the SDRAM controller is ready */
  while(FMC_GetFlagStatus(fmc_bank, FMC_FLAG_Busy) != RESET)
  {}

  /* Send the command */
  FMC_SDRAMCmdConfig(&sdCMD);

  /* Step 4 ------------------------------------------------------------------*/
  /* Insert 100ms delay */
  __Delay(10);

  /* Step 5 ------------------------------------------------------------------*/
  /* Configure a PALL (precharge all) command */
  sdCMD.FMC_CommandMode            = FMC_Command_Mode_PALL;
  sdCMD.FMC_CommandTarget          = target_bank;
  sdCMD.FMC_AutoRefreshNumber      = 1;
  sdCMD.FMC_ModeRegisterDefinition = 0;

  /* Wait until the SDRAM controller is ready */
  while(FMC_GetFlagStatus(fmc_bank, FMC_FLAG_Busy) != RESET)
  {}

  /* Send the command */
  FMC_SDRAMCmdConfig(&sdCMD);

  /* Step 6 ------------------------------------------------------------------*/
  /* Configure an auto-refresh command */
  sdCMD.FMC_CommandMode            = FMC_Command_Mode_AutoRefresh;
  sdCMD.FMC_CommandTarget          = target_bank;
  sdCMD.FMC_AutoRefreshNumber      = 8;
  sdCMD.FMC_ModeRegisterDefinition = 0;
  /* Wait until the SDRAM controller is ready */
  while(FMC_GetFlagStatus(fmc_bank, FMC_FLAG_Busy) != RESET)
  {}

  /* Send the first command */
  FMC_SDRAMCmdConfig(&sdCMD);
  /* Wait until the SDRAM controller is ready */
  while(FMC_GetFlagStatus(fmc_bank, FMC_FLAG_Busy) != RESET)
  {}

  /* Send the second command */
  FMC_SDRAMCmdConfig(&sdCMD);

  /* Step 7 ------------------------------------------------------------------*/
  /* Program the external memory mode register */
  tempr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
                    SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
               SDRAM_MODEREG_CAS_LATENCY_3 |
               SDRAM_MODEREG_OPERATING_MODE_STANDARD |
               SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;

  /* Configure a load Mode register command */
  sdCMD.FMC_CommandMode            = FMC_Command_Mode_LoadMode;
  sdCMD.FMC_CommandTarget          = target_bank;
  sdCMD.FMC_AutoRefreshNumber      = 1;
  sdCMD.FMC_ModeRegisterDefinition = tempr;
  /* Wait until the SDRAM controller is ready */
  while(FMC_GetFlagStatus(fmc_bank, FMC_FLAG_Busy) != RESET)
  {}

  /* Send the command */
  FMC_SDRAMCmdConfig(&sdCMD);

  /* Step 8 ------------------------------------------------------------------*/
  /* Set the refresh rate counter */
  /* (15.62 us x Freq) - 20 */ // IS42S16400J = 1386
 /* (7.81 us  x Freq) - 20 */ // IS42S16320F = 683
  /* Set the device refresh counter */
  //FMC_SetRefreshCount(1386);
 FMC_SetRefreshCount(683);
  /* Wait until the SDRAM controller is ready */
  while(FMC_GetFlagStatus(fmc_bank, FMC_FLAG_Busy) != RESET)
  {}
}

 

The code is working properly for just one SDRAM which is FMC_Bank2_SDRAM when I close the GPIOC_2 and GPIOC_3's alternate function definition and set the functions to work just for FMC_Bank2_SDRAM. The problem occurs at the second loop attempt in the SDRAM_InitSequence line. When PC jumps to first command write line (FMC_SDRAMCmdConfig line in the second attempt), in line 965, which is FMC_Bank5_6->SDCMR = tmpr; is the reason of debug access error. Every time it is corrupted. And now I realized that in this situation the write and read are not completing and core is going fault. Thanks.

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