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Bug Report: HAL_RCC_GetSysClockFreq() does not support PLLMUL value 6.5

Question asked by li.hongliang on Apr 1, 2017
Latest reply on Apr 3, 2017 by li.hongliang

This code snippet is generated by STMCubeMx 4.6.0 and STM32Cube FW_F1 V1.4.0 for STM32F107

 

964 uint32_t HAL_RCC_GetSysClockFreq(void)
965 {
966 #if defined(RCC_CFGR2_PREDIV1SRC)
967 const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
968 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
969 #else
970 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
971 #if defined(RCC_CFGR2_PREDIV1)
972 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
973 #else
974 const uint8_t aPredivFactorTable[2] = { 1, 2};
975 #endif /*RCC_CFGR2_PREDIV1*/

In my setup, I have SYSCLK from PLLCLK which is generated from HSI. When PLLMUL is set to 6.5, HAL_RCC_GetSysClockFreq() will try to access the 13th (0x1101) element which is outside the array. Plus where is 13 from?

 

 

I am working around this problem by setting PLLMUL to 9 in STMCubeMx.

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