AnsweredAssumed Answered

18.4.17 TIMx DMA control register (TIMx_DCR)

Question asked by John Hite on Mar 24, 2017
Latest reply on Mar 30, 2017 by Khouloud G

in RM0090 18.4.17 TIMx DMA control register (TIMx_DCR) it states:

Bits 4:0 DBA[4:0]: DMA base address
This 5-bit vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this
case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.


Does this mean the transfers are overwriting the timer control registers?