Idea for engineers of st.
The dma module has freedom for additional function. To use a status
DMA_Stream_x->CR |= DMA_SxCR_CIRC ////mode of the ring buffer
DMA_Stream_x->CR, Bits 7:6 DIR[1:0]: Data transfer direction = 0x11
The mode the mode of an automatic stop of data transfer on coincidence of number of the NDTR buffer == external number.
In the real implementation - the mode of the ring NDTR buffer it can't be correctly read. I think that dma uses the shadow copy NDTR. It means that NDTR can be used in addition.
The perhaps free address in DMA space (there is a place), or an in-memory address + the link in DMA space.
As it can work.
Game in a game of tag in the ring buffer. here example of
In a case with hardware control of dma - it shouldn't be launched many times. There will be enough one start. The user shouldn't track data transfer - the buffer will work completely automatically. For the user there will be a function with check of the free space in the buffer, and copying of data in the buffer.
Important - filling and sending data can happen at the same time without failures.
DMA can work very quickly in case of data transfer memory memory. He doesn't need to wait.
When there is a sending data - it is necessary to wait for a signal from the periphery. This function at you is already realized.
Option of reception of data in the ring buffer through DMA with DIR[1:0]: Data transfer direction = 0x11.
Perhaps when using the hardware mechanisms of flow control. For example the CTS/RTS lines for USART.
An opportunity to temporarily stop transmission to readiness of a receiving device - will be the useful.
In addition it is necessary to use the free bits of the CR register - for control.
Besides - DMA channels aren't enough.