There appears to be conflicting information in the maximum APB1/APB2 speed on the STM32F411 chip, in both the data sheet and the STM32CUBEMX software. I was hoping someone here may know more about why this is.
In the manual (RM0383), in one place it quite clearly states
The maximum frequency of the AHB domain is 100 MHz. The maximum allowed frequency of the high-speed APB2 domain is 100 MHz. The maximum allowed frequency of the low-speed APB1 domain is 50 MHz.
Then, later on during the register section (RCC->PPRE2), it states
The software has to set these bits correctly not to exceed 84 MHz on this domain.
Similarly, for the low speed APB2 domain, it states:
The software has to set these bits correctly not to exceed 42 MHz on this domain.
Well, which is it? Can I set these to 100/50 MHz or only a max of 84/42 MHz? Anecdotally, I can say that setting them to 100 MHz has not caused me issues so far.
I wouldn't have even noticed it except that in the STM32CUBEMX software, it gives an error if I try to set the APB1 clock above 42 MHz. Interestingly, no such error is given if I set APB2 above 84 MHz.
Anyone have more info on this? There's nothing in the errata list about it. The data sheet is still in its initial version.
Maybe the original intent of the chip was to be run at 84 MHz and they simply didn't update it everywhere?