I work on a SPC560 P40 L3 and I would to capture timestamps on falling edge events on SECSRC "Counter #0 input pin".
I have one square signal mapped on eTimer0 channel 0 on the C pin alternate function.
I could see my signal shift from high state to low state with Trace 32. So I think my signal is correctly mapped to the input.
Here is my eTimer channel 0 configuration :
I have a signal with a 12,5 kHz tick time and a 16 Mhz SYSCLOCK.
Unfortunately, there is no events on CAPT 1 register.
First, I was wondering for some time synchronization issues but when I select "Count rising edges of primary source while secondary input high active" CNTR just stop. So I suspect that the counter #0 input pin is not linked with my input signal. I could manually see values on CAPT 1 when I change SECSRC polarity with the SIPS register, but thats all.
Is there any mistakes with my eTimer configuration register ? I am also wondering how I could synchronize IP bus clock and my sensor signal tick time with just a 128 prescaler.