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STM32F4 PLL I2S continous clock generation

Question asked by Hubert.Hans on Mar 12, 2017
Latest reply on Mar 16, 2017 by Hubert.Hans

i have a question about MCLK and LRCK generation on an STM32F4 system.
I want to connect an Audio ADC to an SPDIF codec which need an continous
Mclk and Lrclock. I have the option to use an external 24.5760 Meg crystal and do
the LRClock phaseadjustment via ttl logic /divider to keep all in sync.
What i need is the I2S_MCLK and I2S_WS (LRCLK) clocks to remain active even when i am
not sending bytes or receive some.
I have not found any information on how to route the PLL clock to an I/O pin.

Is this possible and do i have jitter improvements or should i keep the crystal ?

Big thanks !