I've just assembled and tested (by pin toggling) my custom board.
Initial clock configuration is ok (and I would not recommend using Eclipse plugin, standalone app is way more stable); LED blinker is ok; basic UART configs to see anythiong going from console is ok; now it is time to configure external SDRAM.
I have two 256 Mbit chips in parallel to make 32-bit wide bus - to maximize bandwidth - 64 megabytes total.
As i mentioned before, pin toggle test found no electrical problems - no short or open circuits.
Initial board code is made with help of STM32CubeMX and here is the trouble: pinout, timings and all such things are fine, but default code is NOT enabling SDCLK (which is mapped to PG8, ofc).
When I've added line
FMC_Bank5_6->SDCMR |= FMC_SDCMR_CTB1 | (1); // MODE : 001: clock Configuration Enable
after timing initialization, clock appeared on that pin and now I see data on bus. SDRAM is still not fully functional because refresh is not set yet.
It seems that code produced by STM32CubeMx is not following the initialization sequence, which is described in chapter 13.7.3 of RM