I've recently set about to use the Low Power Timer on an STM32L071. The idea is to set it to count up to a particular value then stop, the code for which follows:
void hal_Timers_LowPower_Once(uint32_t period)
LPTIM1->CR |= LPTIM_CR_ENABLE;
LPTIM1->ARR = period;
while( 0u == (LPTIM1->ISR & LPTIM_ISR_ARROK) );
LPTIM1->ICR = LPTIM_ICR_ARROKCF;
LPTIM1->CR |= LPTIM_CR_SNGSTRT;
while( 0u == (LPTIM1->ISR & LPTIM_ISR_ARRM) );
Before calling this function, the ISR, IER, CFGR, CR, CMP and CNT registers are all 0x00000000 (reset values).
The ARRM flag seems to be set immediately after SNGSTRT is programmed, regardless of the ARR value or clock source. This has happened with 2 MHz, 16 MHz and 32 MHz APB clocks.
If I include this line after setting SNGSTRT:
LPTIM1->ICR = LPTIM_ICR_ARRMCF;
Clearing the ARRM flag *after* it starts, it will operate properly most of the time, but this surely runs the risk of clearing the actual ARR Match event. An interrupt could easily delay that clear.
So what's the deal? ARRM (and CMPM) get set as soon as SNGSTRT is set. Is there a way to prevent this?